An example of the conventional technology regarding such semiconductor memory test system will be explained with reference to FIGS. 3-5. As shown in FIG. 3, the main components of the conventional semiconductor memory test system include a timing generator 10, a pattern generator 20, a wave formatter 30, and a logic comparator 40. Peripheral devices and a tester processor are, however, abbreviated in the drawing for simplicity.
Under this arrangement, the tests for MUT1-MUTn, which are memory devices under test, are conducted by executing the test program. Normally, the semiconductor memory test system tests several memory devices simultaneously in order to improve production efficiency.
The timing generator 10 generates a reference clock and a strobe timing signal. Pursuant to the test program produced in advance, the pattern generator 20 outputs an address signal ADRS, a write data signal WD, a control signal CS, and expected value data ED, which are synchronized with the reference clock from the timing generator 10.
The wave formatter 30 receives the address signal ADRS, the write data signal WD, and the control signal CS from the pattern generator 20 to format the waveforms into test signals, and supplies the test signals to the memories under test MUT1-MUTn. The write and read operation of the test data for the memory devices under test MUT1-MUTn is controlled by the control signal CS.
The logic comparator 40 detects whether there is a match between the data read from the memory devices under test MUT1-MUTn at the timing of the strobe signal STRB from timing generator 10 and the expected value data. The logic comparator 40 determines the pass/fail of the memories devices under test MUT1-MUTn based on the result of the comparison at the cycle of CPE=“1”.
Next, the operation of the logic comparator 40 will be explained with reference to FIG. 4 which shows the basic circuit structure of the logic comparator.
Normally, the logic comparator 40 includes logic comparison circuits 41–4n which correspond to the memory devices under test MUT1-MUTn. Although each of the logic comparison circuits 41–4n in FIG. 4 includes a comparison circuit corresponding to each data bit of the MUT, the data bits here is expressed as one bit in order to simplify the diagram.
In the logic comparison circuit 4n, the test data signal RDn that has been read out from MUTn is latched by a register 60 at the timing of the strobe signal STRB from the timing generator. An EXNOR (exclusive NOR) gate 70 detects whether there is a match between the latched data from the register 60 and the expected value data EXP from the pattern generator. When there is a match, the EXNOR gate 70 generates a match detection signal “1”.
The logic comparison (for determining pass or fail) is conducted by an AND gate 73 at the timing of the CPE signal and the match detection signal noted above provided through an inverter 71. When a mismatch is detected in the cycle of CPE=“1”, the logic comparison circuit determines a failure and outputs a fail detection signal FAIL=“1”. When all the data read out from the memory devices under test MUT1-MUTn match the expected value data, a match flag signal MF is produced by an AND gate 90 and is provided to the pattern generator 20.
Next, the process of testing a flash memory will be explained in the following.
When testing a flash memory, because of its operational principle, data cannot always be set in the target memory cell by one writing or erasing action. Rather, ordinarily, a flash memory requires writing actions or erasing actions of several times. Then, in the memory cell where the writing or erasing operation has been correctly conducted, the memory is so designed that excess writing and erasing actions, which are additional writing and erasing motions with respect to the successful memory cell, are no longer allowed. Further, the required number required for writing or erasing actions varies depending on, such as, the addresses of the flash memory.
One of the types of flash memories having the above characteristic is called a NAND type flash memory. In the NAND flash memory, the internal cells are structured as a unit of page where the writing action is conducted as a unit of page. For example, as shown in FIG. 5, in the memory having memory cells of 1,024 rows by 4,224 columns, each row is considered as one page. Thus, the memory having 1,024 pages is structured from page 1 to page 1,023.
Further, the erasing action in the NAND type flash memory is conducted by a unit of block which is a group of consecutive pages. For example, in the example shown in FIG. 5, four (4) pages of memory cell constitute one block, thus, the flash memory is structured by 0–255 blocks.
In testing a NAND type flash memory having the above characteristic, a match function is used. In the match function, sequence control of the test pattern generation is conducted based on the result of the match signal explained above. When one memory MUT out of plural memories under test MUT1-MUTn shows a mismatch, writing and erasing test is conducted once again with that address of the MUT. At this time, in order to avoid the excess writing and erasing actions towards the MUT's addresses showing the match, a write enable signal to the MUTs is prohibited.
When all the memory devices under test MUT1-MUTn are matched with the expected data, the operation then moves on to the next addresses and begins conducting another writing and erasing test. When mismatch is repeated in the same memory cell for more than a predetermined number of times, the memory under test MUT is determined defective. When the data writing and erasing tests are correctly conducted for all of memory cells of the addresses within the specified number of times, the MUTs will be considered non-defective.
In the NAND type flash memory, when the number of defective blocks is smaller than a predetermined number, the flash memory is considered non-defective, even though a defective block exists therein. This is because a user of the memory recognizes that there are defective blocks in the NAND type flash memory in advance so that he can arrange his design in such a way that the defective blocks will not be used.
Incidentally, when determining the quality of the NAND type flash memory, once a mismatch is detected for a target block of the memory, this block is determined as defective. Thus, there is no need to further continue a logic comparison procedure for the block thereafter. However, the conventional semiconductor memory test system does not includes such a function, therefore, it will continue the logic comparison using the match function even after the defective block is recognized.
Since the conventional semiconductor memory test system continues the logic comparison with use of the match function even after detecting the defective block in the flash memory, a problem arises that unnecessary test times have to be spent in the test.